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Product Information Device Database® Downloads Compliance Testing Distributors |
Toshiba TMPM366FYFGThe Toshiba TMPM366FYFG is an ARM Cortex-M3 microprocessor core Maximum operating frequency: 48 MHz On Chip program memory and data memory Internal FlashROM : 256 Kb Internal SRAM : 48 Kbyte Memory controller Up to 16Mbytes access area (Program / Data) External data bus (Separate / Multiplex): 8/16bit bus width Chip select controller: 2 channels DMA controller: 4 channels Transfer can support on chip Memory / Peripheral I/O / External memory 16-bit timer: 10 channels 16-bit interval timer mode 16-bit event counter mode 16-bit PPG output Input capture function Watchdog timer (WDT): 1 channel Watchdog timer reset UART : 1 channel Supports Full UART / supports IrDA1.0 mode General-purpose serial interface (SIO/UART): 2 channels Either UART mode or synchronous mode can be selected (4byte FIFO equipped: 2ch) Serial bus interface (I2C/SIO): 2 channels Either I2C bus mode or synchronous mode can be selected. Synchronous Serial interface (SSP): 3 channel Communication protocol that includes SPI: 3 types (SPI/SSI/Microwire) Baud rate: Master mode: 12Mbps (max.), Slave mode: 4.0Mbps (max.) USB Device controller : 1channel Compliance USB Specification Rev.2.0. Supports FS (12Mbps) (dose not support LS). 12-bit AD converter (ADC): 12channels Start up with 16-bit timer / Start up with an external trigger input Fixed channel / Channel scan mode Single / repeat mode AD monitog 2ch Conversion speed 1��������µsec. (@fsys = 40MHz) Interrupt source Internal : 50 factors...The order of precedence can be set over 7 levels External : 10 factors...The order of precedence can be set over 7 levels. Non-maskable interrupt (NMI) Input/ output ports (PORT): 74 pins Standby modes: IDLE, STOP1, STOP2 Clock generator (CG) On-chip PLL (8× / 6× ) Clock gear function: The high-speed clock can be divided into 1/1, 1/2, 1/4 or 1/8. Debug interface JTAG / SWD / SWV / TRACE (DATA 4bit).
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