Toshiba TMPM342FYXBG

The Toshiba TMPM342FYXBG is an ARM Cortex-M3 microprocessor core (Little-endian) Maximum operating frequency: 40 MHz Standby modes: IDLE, STOP1, STOP2 On Chip memory RAM : 32 Kbyte (2 Kbyte Backup RAM) Flash ROM : 256 Kbyte DMA controller (DMAC):4ch Transfer mode: Built-in memory, built-in I/O and external memory Programmable Servo Controller (PSC) Instruction RAM=2KB/Data RAM=2KB Supports transfer instruction, arithmetic instruction, shift instruction, logic instruction, compare instruction, branch instruction and control instruction Feasible to boot-up by 16-bit timer Interrupt source Internal: 77 / External: 8 7 priority levels Input/output port: 63 pins Watch-dog timer (WDT): 1 channel 2-phase pulse counter (PHC): 2 channels Frequency counter/phase counter function Supports incremental encoder High resolution PPG output (TMRD): 4+4 channels Duty setting can be set in the 160MHz (6.25nS) units. 16-bit timer (TMRB):10 channels 16-bit interval timer Supports PSC boot-up signal (only ch0) Supports PWM output General-purpose serial interface (SIO/UART):3 channels Selectable UART/synchronous mode Serial bus interface (SBI):1 channel I2C bus mode Variable data SIO/serial bus interface (VSIO):1 channel Edge switching/MSB first or LSB first selectable Data length can be set to 1-bit units from 8- up to 40-bit Synchronous serial interface (SSP): 1 channel 3 kinds of synchronous protocols including SPI 12-bit SAR type A/D converter (SAR ADC): 2 units/8 ch + 4 ch Number of inputs: 8 ch 16-bit A/D converter (ADC):1 unit/4 ch Number of difference inputs: 4ch 10-bit D/A convertor (DAC): 2 units VREFH cutting function Input/output variation settling time: 100 us Clock generator (CG) Built-in PLL (Maximum 160MHz at 16-fold multiplexing) Clock gear function can divide a high-speed clock to 1/1, 1/2, 1/4 or 1/8. Debug interface SWD (DATA TRACE 2-bit).