Silicon Laboratories, Inc. SiM3C144

The Silicon Laboratories, Inc. SiM3C144 is a 32-bit ARM Cortex M3 CPU - 80 MHz maximum frequency - Nested vectored interrupt control (NVIC) with 16 levels of interrupt priority Memory - 32-256 kB Flash; In-system programmable - 8-32 kB SRAM (including 4 kB retention SRAM, which preserves state in sleep mode) - External bus interface supports up to 16 MB of external memory or a parallel LCD interface Clock Sources - Internal oscillator with PLL: 20-80 MHz - Internal 48 MHz oscillator supports crystal-less USB operation - Low-power internal oscillator: 20 MHz - Low-frequency internal oscillator: 16.4 kHz - External oscillator: Crystal, RC, C, CMOS clock 128/192/256-bit Hardware AES Encryption 16/32-bit CRC - Hardware support for four common polynomials Timers/Counters - 2 x 32-bit or 4 x 16-bit timers with capture/compare - 2 x 16-bit, 2 channel counters with capture/compare/PWM - 16-bit, 6-channel counter with capture/compare/PWM and dead-time controller - 16-bit low power timer - 32-bit real time counter (RTC) - Watchdog counter 128-bit Unique ID 2 x 12-Bit Analog-to-Digital Converters (ADC) - Up to 28 channels - Up to 250 ksps 12-bit mode or 1 Msps 10-bit mode - Single, simultaneous, interleaving modes supported 2 x 10-Bit Digital-to-Analog Converter (IDAC) - DMA support for waveform generation 16-Channel Capacitance-to-Digital Converter - Supports buttons, sliders, wheels, and capacitive proximity Two Low-Current Comparators - Integrated 6-bit programmable reference voltage 16-Channel DMA Controller - Supports Peripherals, external triggers, and counters Flexible I/O - Up to 59 contiguous GPIO - Up to 6 programmable high-power capable IO Communication Interfaces - 2 x USARTs and 2 x UARTs with IrDA and ISO7816 smart card support - 3 x SPIs - 2 x I2C - I2S On-Chip Debugging - JTAG and serial wire debug (SWD) - Cortex-M3 embedded trace macrocell (ETM).