Samsung S3FN429

The Samsung S3FN429 is a System and Memory - 32-bit RISC ARM Cortex-M0 Core - Serial Wire Debug (SWD) - 32 KB internal program full flash - 2 KB internal SRAM - Only little-endian - NVIC of Cortex-M0 - Dynamically reconfigurable interrupt priority (four priority levels) - 32 device interrupt vectors - Selectable eight External Interrupts EXI (n) - Programmable eight wake-up sources from stop Clock Manager (CM) - External Main Oscillator Clock (EMCLK) 1 to 12 MHz - Internal Main Oscillator Clock (IMCLK) 40 MHz - Phase-Locked Loop (PLL) control , from 12 to 40 MHz - Clock monitor to detect an external main oscillator failure - Low power mode (IDLE/STOP) by clock gating control - Programmable clock dividers (SDIV and PDIV) - Reset management - Basic timer for reset generation - Input clock source: EMCLK - Input frequency: 1 to 12 MHz - Output frequency: 12 to 40 MHz Watchdog Timer (WDT) - Configurable microcontroller reset event - Programmable 16-bit down counter 16-bit Timer/Counter (TC) - Operation in an interval, capture, match, and overflow or PWM mode - Match and overflow interrupt - Selectable an internal or external clock Pulse Width Modulation (PWM) - 16-bit PWM signal generation - Interval mode - Programmable idle level - Extension PWM function Pulse Position Decoder (PPD) - 3 input signals are: - PHASEA - PHASEB - PHASEZ - Position counter and position capture timer - Speed counter and speed capture timer - Up/Down counter Inverter Motor Controller (IMC) - 3-Phase 16-bit PWM generation - Programmable dead time insertion - Output off-control by fault input signals - ADC conversion start signal generation Universal Synchronous/Asynchronous Receiver/Transmitter (USART) - 5, 6, 7, 8 and 9-bit data length - Programmable baud rate generator - Parity, framing, and overrun error detection - Loop-back mode - Full duplex - Idle flag for J1587 protocol - Smart-card protocol: error signaling and re-transmission Serial Periph.