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Toshiba TMPM343F10XBG

The Toshiba TMPM343F10XBG is an ARM Cortex-M3 microprocessor core (r2p1) - Maximum operating frequency: 50MHz - Little-endian On-chip memory - RAM : up to 64 Kbyte - ROM : up to 1 Mbyte Programmable Servo Controller (PSC) : 4 units DMA controller (DMAC): 3 units/ 6 (2 + 2 + 2) channels - Transfer mode: Built-in memory, internal I/O Clock generator (CG): 2 channels - Clock input from external sources/external oscillation (8MHz to 20MHz) - Installed 2 units of Built-in PLL - Clock gear function: divides high-speed clock into 1/1, 1/2, 1/4, 1/8 or 1/16 Interrupt source (except a watch-dog timer interrupt) - Internal 124 / External 16 - 7 priority levels Input/output ports (PORT): 59 pins 16-bit timer (TMRB): 16 channels - 16-bit interval timer mode - 16-bit programmable rectangular wave output (PPG) mode 16-bit timer with high resolution PPG output (TMRD): 2 units/ 8 (4+4) channels - Phase shift PPG output function - Cycle synchronous signal output function Enhanced 2-phase pulse counter (EPHC): 3 channels - 2-phase counter mode - 1-phase counter mode - Phase differences measurement mode - Frequency measurement mode Watch-dog timer (WDT): 1 channel Serial channel (SIO/UART): 1 channels - Selectable either UART or synchronous mode Asynchronous serial communication interface (UART): 1 channels - Support for UART with flow control Serial interface (TSPI): 5 channels - Supports 2 types of communications such as SPI mode and SIO mode Serial bus interface (I2C): 1 channel - I2C bus mode 12-bit AD converter (ADC): 3 units /16 (8+4+4) channel - Trigger start function: TMRB interrupt - Single/repeat conversion is capable Debug interface - SWD (DATA TRACE 2-bit).

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Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Generic User Guide
1,364,135 bytes
Technical Reference Manual
1,106,603 bytes

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FLASH Utilities
Real-Time OS
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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