Cypress CY8C5265AXI-LP082

The Cypress CY8C5265AXI-LP082 is a System - 32-bit ARM Cortex-M3 CPU core - DC to 67 MHz operation - Flash Patch and Breakpoint (FPB) block - Data Watchpoint and Trace (DWT) generates data trace information - Instrumentation Trace Macrocell (ITM) can be used for printf-style debugging - DWT and ITM blocks communicate with off-chip debug and trace systems via the SWV interface - Single-Wire Debug (SWD) and Single Wire Viewer (SWV) interfaces Memory - Flash Program Memory, up to 256 KB - Multiple Security Features - Up to 64 KB SRAM memory - 128 bytes of Cache Memory - 2-KB EEPROM, 1 million cycles, and 20 years retention - Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces - 24-channel direct memory access (DMA) with multilayer AMBA high-performance bus (AHB) bus access - Programmable chained descriptors and priorities High bandwidth 32-bit transfer support Digital Peripherals - Versatile I/O system - 46 to 70 I/Os (60 GPIOs, 8 SIOs, 2 USBIOs) - Any GPIO to any digital or analog peripheral routability - 20 to 24 programmable logic device (PLD) based universal digital blocks (UDBs) - Full-Speed (FS) USB 2.0 12 Mbps using a 24 MHz external oscillator - Four 16-bit configurable timers, counters, and PWM blocks - 67 MHz, 24-bit fixed point digital filter block (DFB) to implement finite impulse response (FIR) and infinite impulse response (IIR) filters - Library of standard peripherals - 8-, 16-, 24-, and 32-bit timers, counters and PWMs - SPI, UART, and I2C Advanced Peripherals - Cyclic redundancy check (CRC) - Pseudo random sequence (PRS) generator - Local interconnect network (LIN) bus 2.0 - Quadrature decoder - Analog peripherals (2.7 V . VDDA . 5.5 V) - 1.024 V B1 1% internal voltage reference - Configurable delta-sigma ADC with 8- to 20-bit resolution - Sample rates up to 192 ksps - Programmable gain stage: x 0.25 to x16 - 12-bit mode, 192 ksps, 66-dB signal to noise and distortion ratio.