Cadence Design Systems Inc. R8051XC2-A (1 DPTR)

The Cadence Design Systems Inc. R8051XC2-A (1 DPTR) is a flexible configurable, single-clock 8051 compatible IP core with 9.4 to 12.1 times more performance than legacy 80C51 (with Dhrystone v1.1 Benchmark on identical clock speed, depending on the MDU, number of DPTR and auto inc/dec/switch implementation). Optional features: 32 I/O lines, two 16-bit timer/counters, 6 interrupts/2 priority levels, one serial interfaces (UART), 16-bit multiplication-division unit (MDU), multiple DPTR with auto-increment/auto-switch support, power management unit (PMU), internally and externally generated wait states, software reset, program and data memory extension up to 8MB (banking). Optionally available: On-Chip Debug Support for Keil uVision Debugger. The R8051XC IP core can be implemented in FPGA and ASIC. *** This device is configured for 1 DPTR register ***.