Cadence Design Systems Inc. R8051XC2-AF

The Cadence Design Systems Inc. R8051XC2-AF is a fixed configuration, single-clock 8051 compatible IP core with 10.6 times more performance than the legacy 80C51 (with Dhrystone v1.1 Benchmark on identical clock speed). Optional features: 32 I/O lines, two 16-bit timer/counters, 6 interrupts/2 priority levels, one serial interfaces (UART), dual DPTR, power management unit (PMU), internally and externally generated wait states, program and data memory address spaces of 64kB each. Optionally available: On-Chip Debug Support for Keil uVision Debugger. The R8051XC IP core can be implemented in FPGA and ASIC.