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Cadence Design Systems Inc. T8051

The Cadence Design Systems Inc. T8051 is an 8051 compatible IP core with 4 times more performance than the classic 8051. Optional features: 8 I/O lines, one 16-bit timer/counter, 11 interrupts/4 priority levels, one serial interface (UARTs), power management unit (PMU), Optionally available: On-Chip Debug Support for Keil uVision Debugger. The T8051 IP core can be implemented in FPGA and ASIC.

[Chip Vendor] [Distributors]
Development Tools
Compiler, Assembler, Linker, Debugger
Data Sheets
Data Sheet
120,090 bytes

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Header Files
Emulators
Real-Time OS
Simulated Features

The following on-chip peripherals are simulated by the Keil Software µVision Debugger.

AGSI Drivers

The following AGSI Drivers are available for the Keil Software µVision Simulator.

AGDI Drivers

The following AGDI Drivers are available for the Keil Software µVision Debugger.

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