Peripheral Simulation

For Silicon Laboratories, Inc. C8051F300 — Crossbar

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Crossbar Dialog

The Crossbar dialog displays and configures the simulation of the Crossbar peripheral pin assignment capability. The controls in this dialog are separated into three logical groups:

Crossbar Register 0 XBR0 (Port I/O Crossbar Register 0) contains the following control bit settings:

• XSKPn (Crossbar Skip Enable Bits 6-0) selects the port 0.n pins that are skipped by the Crossbar decoder.

Crossbar Register 1 XBR1 (Port I/O Crossbar Register 1) contains the following control bit settings:

• CP0AEN (Comparator 0 Asynchronous Output Enable0) is set to route Asynchronous CP0 to a port pin.
• CP0OEN (Comparator 0 Output Enable) is set to route CP0 to a port pin.
• SYSCKE (SYSCLK Output Enable Bit) is set to route SYSCLK to a port pin.
• SMB0EN (SMBus0 Bus I/O Enable Bit) is set to route SMBus0 signals SDA and SCL to 2 port pins.
• URX0EN (UART RX Enable) is set to route UART0 RX to pin P0.5.
• UTX0EN (UART TX Enable) is set to route UART0 TX to pin P0.4.

Crossbar Register 2 XBR2 (Port I/O Crossbar Register 2) contains the following control bit settings:

• WEAKPUD (Weak Pull-Up Disable Bit) is set to disable weak pull-ups.
• XBARE (Crossbar Enable Bit) is set to enable Crossbar decoding.
• T1E (T1 Input Enable Bit) is set to route T1 to a port pin.
• T0E (T0 Input Enable Bit) is set to route T0 to a port pin.
• ECIE (PCA0 Counter Input Enable Bit) is set to route ECI to a port pin.