Peripheral Simulation

For Atmel AT91M42800A — Power Management Controller

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.
• VTREGs (Virtual Target Registers) which support I/O with the peripheral.

These simulation capabilities are described below.

Power Management Controller Dialog

The Power Management Controller Dialog configures the power saving mode of the ARM controller by enabling and disabling the system and peripheral clocks.

System & Peripheral Clock Group

• The CPU box, if checked, stops the system clock, and forces the processor into Idle mode.
• PMC_SCSR (System Clock Status Register) displays the status of the CPU clock.
• PMC_PCSR (Peripheral Clock Status Register) displays the current status of the peripheral clock.
• US0 if set, enables the USART 0 clock.
• US1 if set, enables the USART 1 clock.
• US2 if set, enables the USART 2 clock.
• SPIA if set, enables the Serial Peripheral Interface A clock.
• SPIB if set, enables the Serial Peripheral Interface B clock.
• TC0 if set, enables the Timer/Counter 0 clock.
• TC1 if set, enables the Timer/Counter 1 clock.
• TC2 if set, enables the Timer/Counter 2 clock.
• TC3 if set, enables the Timer/Counter 3 clock.
• TC4 if set, enables the Timer/Counter 4 clock.
• TC5 if set, enables the Timer/Counter 5 clock.
• PIOA if set, enables the parallel I/O A clock.
• PIOB if set, enables the parallel I/O B clock.

Clock Generator Mode Group

• PMC_CGMR (Clock Generator Mode Register) displays the composite value of the following clock generator components:
• MUL (Phase Lock Loop Factor) is the multiplication ratio from 1 to 63. A value of 0 deactivates the Phase Locked Loop.
• PLLCOUNT (PLL Lock Counter) is the number of 32,768 Hz clock cycles before the PLL is locked.
• MCKOSS (Master Clock Output Source Selection) selects the type of clock (slow clock, master clock, master clock inverted or master clock/2).
• PRES (Prescaler Selection) selects the scaling factor for the selected clock.
• MCKODS (Master Clock Output Disable) If set, the master clock output MCKO pin is tri-stated. If not set, MCKO is driven from the master clock (MCO).
• PLLS (PLL Selection) selects the frequency range for the PLL source.
• CSS (Clock Source Selection) if set, the clock source is the PLL output. If reset, the clock source is the slow clock.
• XTAL is the oscillator frequency.
• CLOCK is the master clock frequency.

Interrupt Mask & Status Group

• PMC_IMR (Interrupt Mask Register) displays the main oscillator and PLL Lock interrupt mask settings.
• PMC_SR (Status Register) displays the main oscillator (MOSCS) and PLL Lock Status (LOCK).
• LOCK (PLL Lock Interrupt Disable) If set, disables the PLL Lock interrupt.

XTAL VTREG
Data Type: unsigned long

The XTAL VTREG contains the frequency of the oscillator (in Hertz) used to drive the microcontroller. The value is automatically set from the value specified in Project Options - Options for Target. However, you may change the value of XTAL using the command window. For example:

XTAL=33000000

You may also output the current value of XTAL using the following:

XTAL

XTAL may be used in calculations to synchronize external scripts with the simulated microcontroller.