Peripheral Simulation

For Dallas Semiconductor DS80C410 — Math Accelerator Unit

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Math Accelerator Unit Dialog

The Math Accelerator Unit dialog displays and allows you to specify the configuration for the Arithmetic Accelerator.

Control & Status

• MCNT1 (Multiplier Control Register 1) contains the following bit settings:
• MST (Multiply/Accumulate Status Flag) is set while the MAU is performing an arithmetic operation.
• MOF (Multiply Overflow Flag) is set on division by zero or when the resulting product exceeds 0xFFFF.
• SCB (Shift Carry Bit) is used as the carry bit for shift operations when the Shift Carry Enable (SCE) bit is set.
• CLM (Clear Accelerator Registers) is set to clear the MA, MB and MC registers.
• MCNT0 (Multiplier Control Register 0) contains the following bit settings:
• MAS (Multiplier Register Shift Bits) determines the number of shifts to perform on shit operations.
• LSHIFT# (Left Shift) is set to shift bits from the least to most significant bit positions. If reset, bit shift from most to least significant positions.
• CSE (Circular Shift Enable) is set to wrap shifted bits.
• SCE (Shift Carry Enable) is set to include the carry bit in a shift operation.
• Operation displays the arithmetic operation requested.

Source/Result Registers

• MA (Multiplier A Register) holds the 32-bit divisor for division and the 32-bit multiplicand for multiplication operations. It returns the 32-bit quotient for divide operations and 32-bit product for multiplication operations. Results for shift operations are also returned in this register.
• MB (Multiplier B Register) holds the 32-bit dividend for divide operations and the 32-bit multiplier for multiplication operations. It returns the remainder for divide operations.
• Note: The MA and MB registers can receive or hold up to a 32-bit value, accessed via a series of 4 sequential writes to or reads from the register.

Accumulator Register

• MC (Multiplier C Register) is a 40-bit accumulator. The result of the last multiply or divide operation is always added to this register. It is not affected by shift or normalize operations.
• Note: The MC register can receive or hold up to a 40-bit value, accessed via a series of 5 sequential writes to or reads from the register.