Peripheral Simulation

For NXP (founded by Philips) LPC2141 — Phase Locked Loops (PLL0-1)

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Phase Locked Loop 0 Dialog

The Phase Locked Loop 0 Dialog controls Phase Locked Loop (PLL) function of the ARM controller. Using this dialog, you can configure the MCU clock frequency by changing the multiplier and divider values that control the MCU clock.

Control Register

• PLL0CON (PLL Control Register) contains the PLL Enable bit (bit 0), and the PLL Connect bit (bit 1).
• PLLE (PLL Enable) is set to activate the PLL and allow it to lock to the requested frequency.
• PLLC (PLL Connect) is set to connect the PLL as the clock source. A successful connect requires the PLLE bit set.

Configuration Register

• PLL0CFG (PLL Configuration Register) contains the PLL Multiplier (MSEL) and PLL Divider (PSEL) values.
• MSEL (PLL Multiplier Value) is the multiplier value used in calculating the PLL clock frequency.
• PSEL (PLL Divider Value) is the divider value used in calculating the PLL clock frequency.

Status Register

• PLL0STAT (PLL Status Register) contains the following PLL status bits:
• MSEL (PLL Multiplier Read-Back Value) is the multiplier value currently used by the PLL.
• PSEL (PLL Divider Read-Back Value) is the divider value currently used by the PLL.
• PLLE (PLL Enable Read-Back Value) is set when the PLL is active. If reset, the PLL is turned off.
• PLLC (PLL Connect Read-Back Value) is set when the MCU uses the PLL as the clock source. If reset, the MCU uses the oscillator clock as the source.
• PLOCK (PLL Lock Status) is set when the PLL is locked on the requested frequency.

Feed Register

• PLL0FEED (PLL Feed Register) contains the 8-bit value last written to this register. To set the clock configuration, this register must be stored with consecutive values of 0xAA and 0x55, while the PLLE and PLLC bits are enabled.

Crystal Oscillator & Processor Clock

• XTAL (Crystal Oscillator Frequency) the frequency (in MHz) of the crystal oscillator.
• CLOCK (Processor Clock) is the computed processor clock frequency (CCLK) in MHz.

Phase Locked Loop 1 Dialog

The Phase Locked Loop 1 Dialog controls Phase Locked Loop (PLL) function of the ARM controller. Using this dialog, you can configure the MCU clock frequency by changing the multiplier and divider values that control the MCU clock.

Control Register

• PLL1CON (PLL Control Register) contains the PLL Enable bit (bit 0), and the PLL Connect bit (bit 1).
• PLLE (PLL Enable) is set to activate the PLL and allow it to lock to the requested frequency.
• PLLC (PLL Connect) is set to connect the PLL as the clock source. A successful connect requires the PLLE bit set.

Configuration Register

• PLL1CFG (PLL Configuration Register) contains the PLL Multiplier (MSEL) and PLL Divider (PSEL) values.
• MSEL (PLL Multiplier Value) is the multiplier value used in calculating the PLL clock frequency.
• PSEL (PLL Divider Value) is the divider value used in calculating the PLL clock frequency.

Status Register

• PLL1STAT (PLL Status Register) contains the following PLL status bits:
• MSEL (PLL Multiplier Read-Back Value) is the multiplier value currently used by the PLL.
• PSEL (PLL Divider Read-Back Value) is the divider value currently used by the PLL.
• PLLE (PLL Enable Read-Back Value) is set when the PLL is active. If reset, the PLL is turned off.
• PLLC (PLL Connect Read-Back Value) is set when the MCU uses the PLL as the clock source. If reset, the MCU uses the oscillator clock as the source.
• PLOCK (PLL Lock Status) is set when the PLL is locked on the requested frequency.

Feed Register

• PLL1FEED (PLL Feed Register) contains the 8-bit value last written to this register. To set the clock configuration, this register must be stored with consecutive values of 0xAA and 0x55, while the PLLE and PLLC bits are enabled.

Crystal Oscillator & Processor Clock

• XTAL (Crystal Oscillator Frequency) the frequency (in MHz) of the crystal oscillator.
• CLOCK (Processor Clock) is the computed processor clock frequency (CCLK) in MHz.