Peripheral Simulation

For NXP (founded by Philips) LPC2102 — APB Divider

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

APB Divider Dialog

The APB Divider Dialog controls APBDIV resiter. This register controls the ABP clock rate (PCLK) based on the MPU clock rate (CCLK). You may display or change the settings using this dialog.

APB Divider

• APBDIV (APB Divider Control Register) contains the bit settings that determine the MPU clock (CCLK) divisor for calculating the peripheral clock (PCLK). Use the list box to select the clock divider.