Peripheral Simulation

For STMicroelectronics STR735FZ2 — APB Bridges 0-1

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

APB Bridge Dialog

The APB Bridge dialog displays and configures the Advanced Peripheral Bus Bridge. The controls in this dialog are separated into several logical groups.

Peripheral Management

• PCG0 (Peripheral Clock Gate 0) is checked to allow the System clock to be connected to the selected peripheral. When switched off, the peripheral is reset.
• PCGB0 (Peripheral Clock Gating Bit 0) is used to switch the System clock off and on without resetting the selected peripheral.
• CFG_PCGR0 (Peripheral Clock Gating Register 0) contains the current PCG0 peripheral bit settings.
• CFG_PCGRB0 (Peripheral Clock Gating Register 0) contains the current PCGB0 peripheral bit settings.

Status & Memory

• APB0_BSR (APB Bridge Status Register) contains the error status bits when a time-out, out-of memory or abort condition occurs on the APB.
• APB0_OMR (APB Out of Memory Register) contains the address of the peripheral that attempted to address reserved memory.

Time-out

• APB0_TOR (APB Bridge Time-out Register) enables the abort generation on the ARM7TDMI bus in case of an APB Time-out or out-of memory condition, and a time-out counter which allows a delay before setting the time-out error flag.
• APB0_TOER (APB Time-out Error Register) contains the address of the peripheral that caused the time-out.