Peripheral Simulation

For Infineon XC164S-32F — CPU Configuration

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

CPU Configuration Dialog

The CPU Configuration dialog displays and allows you to edit the configuration of the built-in CPU controls. The controls in this dialog are separated into several logical groups.

CPU Control 1

• CPUCON1 (CPU Control Register 1) contains the following control bit settings:
• VECSC (Vector Table Scaling Factor) sets the spacing (in number of words) between two vectors.
• WDTCTL (Watchdog Timer Control) is set to allow the watchdog timer to enabled or disabled at any time. If reset, disable is only allowed prior to End of Init.
• SGTDIS (Segmentation Disable) is set to disable segmentation.
• INTSCXT (Interruptibility of Switch Context) is set to allow context switches to be interrupted.
• BP (Branch Prediction Unit) is set to enable branch prediction.
• ZCJ (Zero Cycle Jump Function) is set to allow Zero-cycle branch execution.

CPU Control 2

• CPUCON2 (CPU Control Register 2) contains the following control by settings:
• FIFODEPTH (FIFO Depth) sets the number of FIFO entries from none to eight.
• FIFOFED (FIFO Fed) enables the FIFO and selects one, two or three instructions to be fed into the FIFO per cycle.
• BYPPF (Prefetch Bypass) enables the prefetch-to-decode bypass path.
• BYPF (Fetch Bypass) enables the fetch-to-decode bypass path.
• EIOIAEN (Early IO Injection Acknowledge Enable) is set to guarantee injection acknowledge by destructive read.
• STEN (Stall Instruction Enable) is set to enable stall debug instructions.
• LFIC (Linear Follower Instruction Cache) is set to enable the Linear Follower Instruction Cache.
• OVRUN (Pipeline Control) is set to allow overrun of instruction execution pipeline gaps.
• RETST (Return Stack) is set to enable the Return Stack
• DAID (Atomic Injection Deny) is set to deny an injection request during an Atomic instruction.
• SL (Short Loop Mode) is set to enable short loop mode.