Peripheral Simulation

For Atmel AT91SAM7X128 — Watchdog Timer

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Watchdog Timer Dialog

The Watchdog Timer Dialog shows the current state of the on-chip Watchdog Timer. You can change watchdog settings using the controls in this dialog.

Control

• WDT_CR (Control Register) holds the Watchdog Timer restart WDRSTT bit.
• WDRSTT (Watchdog Restart) restarts the watchdog timer.

Mode

• WDT_MR (Mode Register) holds the parameters that control what happens when a timer underflow occurs. They are:
• WDV (Watchdog Counter Value) holds the 12-bit watchdog count value.
• WDD (Watchdog Delta Value) configures the range value to allow a watchdog timer reset to occur.
• Timer displays the current value of the watchdog timer.
• WDFIEN (Watchdog Fault Interrupt Enable) triggers an interrupt when the watchdog timer underflows.
• WDRSTEN (Watchdog Reset Enable) triggers a Watchdog Reset.
• WDRPROC (Watchdog Reset Processor) resets the processor when a watchdog timer underflows.
• WDDIS (Watchdog Disable) disables the watchdog timer.
• WDDBGHLT (Watchdog Debug Halt) stops the watchdog timer when the processor is in Debug mode.
• WDIDLEHLT (Watchdog Idle Halt) stops the watchdog time when the processor is in Idle mode.

Status Group

• WDT_SR (Status Register) holds the WDUNF and WDERR values.
• WDUNF (Watchdog Underflow) is set when at least one watchdog timer underflow occurred since the last read of WDT_SR.
• WDERR (Watchdog Error) is set when at least one watchdog timer error occurred since the last read of WDT_SR.