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Peripheral Simulation
For Atmel AT91SAM9260 — Timer Counters 0-1 (3 Channels)
Simulation support for this peripheral or feature is comprised of:
- Dialog boxes which display and allow you to change peripheral configuration.
These simulation capabilities are described below.
Timer Counter Block 0 Dialog
The Timer/Counter Block Dialog displays and changes the settings
associated with a Timer/Counter Block. Timer/counters perform various
event counting and measurement tasks.
Block & Control Mode
- SYNC creates a synchronization input signal.
-
TC0XC0S defines the external clock input signal for this
Timer/Counter.
Selected Channel Control
-
TC0_CCR displays the Timer/Counter Channel Control
Register.
- SWTRG performs a software trigger.
- CLKDIS disables the clock.
- CLKEN enables the clock.
Selected Channel Mode
-
TC0CMR displays the Timer/Counter Capture Mode
Register.
- WAVE enables Waveform mode.
- CPCTRG resets the counter and starts the clock.
-
TCCLKS selects the source and time base of the clock
signal.
-
CKLI (Clock Invert) increments the falling edge of the
clock.
-
BURST gates the clock by a selected external
signal.
-
ABETRG (TIOA/TIOB External Trigger) uses TIOA as an
external trigger when checked. Uses TIOB when not checked.
-
LDBSTOP stops the counter clock when RB loading
occurs.
-
LDBDIS disables the counter clock when RB loading
occurs.
-
ETRGEDG selects the rising edge, falling edge or both
for an external trigger.
-
LDRA selects loading of register A on the rising edge of
TIOA, falling edge or both.
-
LDRB selects loading of register B on the rising edge of
TIOA, falling edge or both.
Selected Channel Counter Value & Compare/Capture
Registers
- TC0_CV holds the Timer/Counter value.
- TC0_RA holds the Timer/Counter Register A value.
- TC0_RB holds the Timer/Counter Register B value.
- TC0_RC holds the Timer/Counter Register C value.
Selected Channel Interrupt Mask & Status
-
TC0_IMR displays the Timer/Counter Interrupt Mask
Register.
- TC0_SR displays the Timer/Counter Status Register.
-
MTIOB (TIOB Mirror) if set, TIOB is high and if WAVE is
set, TIOB is driven high.
-
MTIOA (TIOA Mirror) if set, TIOA is high and if WAVE is
set, TIOA is driven high.
- CLKSTA (Clock Status) if set, clock is enabled.
-
ETRGS is set if an external trigger occurred after
reading the Status Register.
-
LDRBS is set if register B loading occurred after
reading the Status Register.
-
LDRAS is set if register A loading occurred after
reading the Status Register.
-
CPCS is set if register C compare occurred after reading
the Status Register.
-
CPBS is set if register B compare occurred after reading
the Status Register.
-
CPAS is set if register A compare occurred after reading
the Status Register.
-
LOVRS is set if registers A or B were loaded 2 or more
times but not read after reading the Status Register.
-
COVFS is set if a counter overflowed after reading the
Status Register.
I/O Pins
- TCLK0 is the Timer 0 Clock signal input.
- TCLK1 is the Timer 1 Clock signal input.
- TCLK2 is the Timer 2 Clock signal input.
- TIOA0 is the Timer 0 Signal A input.
- TIOA1 is the Timer 1 Signal A input.
- TIOA2 is the Timer 2 Signal A input.
- TIOB0 is the Timer 0 Signal B input.
- TIOB1 is the Timer 1 Signal B input.
- TIOB2 is the Timer 2 Signal B input.
Timer Counter Block 1 Dialog
The Timer/Counter Block Dialog displays and changes the settings
associated with a Timer/Counter Block. Timer/counters perform various
event counting and measurement tasks.
Block & Control Mode
- SYNC creates a synchronization input signal.
-
TC3XC0S defines the external clock input signal for this
Timer/Counter.
Selected Channel Control
-
TC3_CCR displays the Timer/Counter Channel Control
Register.
- SWTRG performs a software trigger.
- CLKDIS disables the clock.
- CLKEN enables the clock.
Selected Channel Mode
-
TC3CMR displays the Timer/Counter Capture Mode
Register.
- WAVE enables Waveform mode.
- CPCTRG resets the counter and starts the clock.
-
TCCLKS selects the source and time base of the clock
signal.
-
CKLI (Clock Invert) increments the falling edge of the
clock.
-
BURST gates the clock by a selected external
signal.
-
ABETRG (TIOA/TIOB External Trigger) uses TIOA as an
external trigger when checked. Uses TIOB when not checked.
-
LDBSTOP stops the counter clock when RB loading
occurs.
-
LDBDIS disables the counter clock when RB loading
occurs.
-
ETRGEDG selects the rising edge, falling edge or both
for an external trigger.
-
LDRA selects loading of register A on the rising edge of
TIOA, falling edge or both.
-
LDRB selects loading of register B on the rising edge of
TIOA, falling edge or both.
Selected Channel Counter Value & Compare/Capture
Registers
- TC3_CV holds the Timer/Counter value.
- TC3_RA holds the Timer/Counter Register A value.
- TC3_RB holds the Timer/Counter Register B value.
- TC3_RC holds the Timer/Counter Register C value.
Selected Channel Interrupt Mask & Status
-
TC3_IMR displays the Timer/Counter Interrupt Mask
Register.
- TC3_SR displays the Timer/Counter Status Register.
-
MTIOB (TIOB Mirror) if set, TIOB is high and if WAVE is
set, TIOB is driven high.
-
MTIOA (TIOA Mirror) if set, TIOA is high and if WAVE is
set, TIOA is driven high.
- CLKSTA (Clock Status) if set, clock is enabled.
-
ETRGS is set if an external trigger occurred after
reading the Status Register.
-
LDRBS is set if register B loading occurred after
reading the Status Register.
-
LDRAS is set if register A loading occurred after
reading the Status Register.
-
CPCS is set if register C compare occurred after reading
the Status Register.
-
CPBS is set if register B compare occurred after reading
the Status Register.
-
CPAS is set if register A compare occurred after reading
the Status Register.
-
LOVRS is set if registers A or B were loaded 2 or more
times but not read after reading the Status Register.
-
COVFS is set if a counter overflowed after reading the
Status Register.
I/O Pins
- TCLK3 is the Timer 3 Clock signal input.
- TCLK4 is the Timer 4 Clock signal input.
- TCLK5 is the Timer 5 Clock signal input.
- TIOA3 is the Timer 3 Signal A input.
- TIOA4 is the Timer 4 Signal A input.
- TIOA5 is the Timer 5 Signal A input.
- TIOB3 is the Timer 3 Signal B input.
- TIOB4 is the Timer 4 Signal B input.
- TIOB5 is the Timer 5 Signal B input.
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