Peripheral Simulation

For NXP (founded by Philips) LPC2138/01 — VPB Divider

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.
• VTREGs (Virtual Target Registers) which support I/O with the peripheral.

These simulation capabilities are described below.

VPB Divider Dialog

The VPB Divider Dialog controls the VLSI Peripheral Bus Divider control register. This register controls the VBP clock rate (PCLK) based on the MPU clock rate (CCLK). You may display or change the settings using this dialog.

VPB Divider

• VPBDIV (VPB Divider Control Register) contains the bit settings that determine the MPU clock (CCLK) divisor for calculating the peripheral clock (PCLK). Use the list box to select the clock divider.

CLOCK VTREG
Data Type: unsigned long

The CLOCK VTREG contains the speed of the microcontroller instruction clock (in Hertz). This is effectively the number of 1-cycle instructions that the simulated microcontroller can execute each second. This number is derived by dividing the oscillator frequency (specified by the XTAL VTREG) by a fixed number. CLOCK is a read-only VTREG. It may not be changed directly. It changes when the value of the XTAL VTREG or the clock divisor (which is not available on all devices) changes.

XTAL VTREG
Data Type: unsigned long

The XTAL VTREG contains the frequency of the oscillator (in Hertz) used to drive the microcontroller. The value is automatically set from the value specified in Project Options - Options for Target. However, you may change the value of XTAL using the command window. For example:

XTAL=33000000

You may also output the current value of XTAL using the following:

XTAL

XTAL may be used in calculations to synchronize external scripts with the simulated microcontroller.