Peripheral Simulation

For Toshiba TMPA910CRAXBG — Power Management Controller

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Power Management Controller Dialog

The Power Management Controller Dialog configures the power saving mode of the ARM controller by enabling and disabling the system and peripheral clocks.

System & Peripheral Clock

• PMC_SCSR (System Clock Status Register) displays the status of the CPU clock.
• PMC_PCSR (Peripheral Clock Status Register) displays the current status of the processor and peripheral clocks.
• PCK if set, enables the processor clock.
• PCK0 if set, enables programmable clock 0.
• PCK1 if set, enables programmable clock 1.
• PCK2 if set, enables programmable clock 2.
• UDP if set, enables the 48 MHz clock of the USB Device Port.
• PIDn if set, enables peripheral clock n.

Clock Generator

• CKGR_MOR (Main Oscillator Register) displays the composite value of the following components of the main oscillator:
• OSCOUNT (Main Oscillator Start-up Time) contains the number of slow clock cycles multiplied by 8 that represent the time to start up the Main Oscillator.
• MOSCEN (Main Oscillator Enable) if set, enables the main oscillator.
• OSBYPASS (Oscillator Bypass) if set, bypasses the main oscillator. XIN must be connected to an external clock.
• CKGR_MCFR (Main Clock Frequency Register) displays the composite value of the following components:
• MAINF (Main Clock Frequency) contains the number of Main Clock cycles within 16 Slow Clock periods.
• MAINRDY (Main Clock Ready) if set, the Main Oscillator is enabled and the Main Clock Frequency MAINF is valid.
• MAINCK (Main Clock) contains the Main Clock frequency in MHz.
• CKGR_PLLR (PMC Clock Generator PLL Register) displays the composite value for the following:
• PLLCOUNT (PLL Lock Counter) is the number of Slow Clock cycles before the PLL is locked.
• OUT (PLL Clock Frequency Range) selects the PLL clock frequency range in MHz.
• MUL (PLL Multiplier) is multiplied by the selected clock.
• DIV (PLL Divider) is divided into the selected clock.
• USBDIV (Divider for USB Clock) sets the divider output to the PLL clock, the PLL clock divided by 2 or the PLL clock divided by 4.
• SLCK (Slow Clock Frequency) contains the Slow Clock frequency in MHz.
• PLLCK (PLL Clock Frequency) contains the PLL Clock frequency in MHz.
• UDPCK (UPD Clock Frequency) contains the UPD Clock frequency in MHz.

Master Clock

• PMC_MCKR (Master Clock Register) displays the composite value of the following components:
• CSS (Master Clock Source Selection) selects the type of clock (Slow Clock, Main Clock or PLL Clock).
• PRES (Prescaler Selection) selects the scaling factor for the selected clock.
• MCK (Master Clock Frequency) contains the Master Clock frequency in MHz.

Programmable Clock

• Select (Programmable Clock Selection) selects programmable clock 0-2.
• PMC_PCKn (Programmable Clock Register) displays the composite value of the following components:
• CSS (Programmable Clock Source Selection) selects the type of clock (Slow Clock, Main Clock or PLL Clock) used for the selected Programmable clock n.
• PRES (Prescaler Selection) selects the scaling factor for Programmable Clock n.
• PCKn (Programmable Clock Frequency) displays the frequency in MHz for the selected Programmable Clock n.

Interrupt Mask & Status

• PMC_IMR (Interrupt Mask Register) displays the main oscillator and PLL Lock interrupt mask settings.
• PMC_SR (Status Register) displays the main oscillator (MOSCS) and PLL Lock Status (LOCK).
• MOSCS (Master Oscillator Status Interrupt Enable) If set, enables the Master Oscillator interrupt.
• LOCK (PLL Lock Interrupt Disable) If set, disables the PLL Lock interrupt.
• MCKRDY (Master Clock Ready Interrupt Disable) If set, enables the Master Clock Ready interrupt.
• PCKRDYn (Programmable Clock n Ready Interrupt Disable) If set, enables the Programmable Clock n Ready interrupt.