Peripheral Simulation

For CAST, Inc. R8051XC2 — Serial Peripheral Interface (SPI)

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Serial Peripheral Interface Dialog

The Serial Peripheral Interface Dialog controls the Synchronous Serial Channel (SSC) unit of the R8051XC microcontroller. It supports half or full duplex operation. The application software can use this interface to interconnect with other microcontrollers in a master/slave architecture.

Control

• SPCON (SPI Control Register) contains the control flags that setup the SPI mode and baud rate.
• SPEN (SPI System Enable) is set enable the SPI unit.
• MSTR (Master Mode Selection) is set to configure this unit as the master unit. If reset, it is configured as a slave unit.
• CPOL (Clock Polarity) is set to configure the shift clock's idle state to high. If reset, the clock's idle state is low.
• CPHA (Clock Phase) is set to shift data out on the 1st clock edge, then sample data in on the second edge. It is reset to sample data in on the 1st edge, and shift data out on the second edge.
• Clock Rate selects the oscillator frequency divisor used to generate the baud rate.
• SPI Master Clock is the master clock output or slave clock input, depending on the setting of MSTR.

Status

• SPSTA (SPI Status Register) contains the status values for the following bits:
• SPIF (SPI Transfer Complete) is set when the SPI completes a data transfer operation. This bit clears after this register and the data register (SPDAT) are read.
• WCOL (Write Collision Detected) is set when the SPDAT is written while an SPI transfer is still in progress.
• SSERR (Sync Slave Error)
• MODF (Mode Fault)

Slave Select

• SPSSN (SPI Slave Select Input Register) contains the following bits:
• SSDIS (Slave Select Disable)
• SSN (Slave Select Input)

Data

• SPDAT (SPI Data Register) contains the data to be transmitted or received.