Peripheral Simulation

For NXP (founded by Philips) LPC11C22/301 — VPB Divider

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

VPB Divider Dialog

The VPB Divider Dialog controls the VLSI Peripheral Bus Divider control register. This register controls the VBP clock rate (PCLK) based on the MPU clock rate (CCLK). You may display or change the settings using this dialog.

VPB Divider

• VPBDIV (VPB Divider Control Register) contains the bit settings that determine the MPU clock (CCLK) divisor for calculating the peripheral clock (PCLK). Use the list box to select the clock divider.