Peripheral Simulation

For NXP (founded by Philips) LPC11D14/302 — Flash Memory IAP

Simulation support for this peripheral or feature is comprised of:

• Accurate simulation of special on-chip features.

These simulation capabilities are described below.

Flash Memory IAP

The on-chip boot loader code supports 2 Flash memory interfaces:

• In-System Programming (ISP) programs Flash memory via the UART.
• In Application Programming (IAP) erases or modifies Flash memory from the user's application code.