IRQ Mode Bit-Masks

Configure interrupt line mode. More...

Macros
#define	IRQ_MODE_TRIG_LEVEL   (0x00UL /*<< IRQ_MODE_TRIG_Pos*/)
	Trigger: level triggered interrupt. More...
#define	IRQ_MODE_TRIG_LEVEL_LOW   (0x01UL /*<< IRQ_MODE_TRIG_Pos*/)
	Trigger: low level triggered interrupt. More...
#define	IRQ_MODE_TRIG_LEVEL_HIGH   (0x02UL /*<< IRQ_MODE_TRIG_Pos*/)
	Trigger: high level triggered interrupt. More...
#define	IRQ_MODE_TRIG_EDGE   (0x04UL /*<< IRQ_MODE_TRIG_Pos*/)
	Trigger: edge triggered interrupt. More...
#define	IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/)
	Trigger: rising edge triggered interrupt. More...
#define	IRQ_MODE_TRIG_EDGE_FALLING   (0x06UL /*<< IRQ_MODE_TRIG_Pos*/)
	Trigger: falling edge triggered interrupt. More...
#define	IRQ_MODE_TRIG_EDGE_BOTH   (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
	Trigger: rising and falling edge triggered interrupt. More...
#define	IRQ_MODE_TYPE_IRQ   (0x00UL << IRQ_MODE_TYPE_Pos)
	Type: interrupt source triggers CPU IRQ line. More...
#define	IRQ_MODE_TYPE_FIQ   (0x01UL << IRQ_MODE_TYPE_Pos)
	Type: interrupt source triggers CPU FIQ line. More...
#define	IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)
	Domain: interrupt is targeting non-secure domain. More...
#define	IRQ_MODE_DOMAIN_SECURE   (0x01UL << IRQ_MODE_DOMAIN_Pos)
	Domain: interrupt is targeting secure domain. More...
#define	IRQ_MODE_CPU_ALL   (0x00UL << IRQ_MODE_CPU_Pos)
	CPU: interrupt targets all CPUs. More...
#define	IRQ_MODE_CPU_0   (0x01UL << IRQ_MODE_CPU_Pos)
	CPU: interrupt targets CPU 0. More...
#define	IRQ_MODE_CPU_1   (0x02UL << IRQ_MODE_CPU_Pos)
	CPU: interrupt targets CPU 1. More...
#define	IRQ_MODE_CPU_2   (0x04UL << IRQ_MODE_CPU_Pos)
	CPU: interrupt targets CPU 2. More...
#define	IRQ_MODE_CPU_3   (0x08UL << IRQ_MODE_CPU_Pos)
	CPU: interrupt targets CPU 3. More...
#define	IRQ_MODE_CPU_4   (0x10UL << IRQ_MODE_CPU_Pos)
	CPU: interrupt targets CPU 4. More...
#define	IRQ_MODE_CPU_5   (0x20UL << IRQ_MODE_CPU_Pos)
	CPU: interrupt targets CPU 5. More...
#define	IRQ_MODE_CPU_6   (0x40UL << IRQ_MODE_CPU_Pos)
	CPU: interrupt targets CPU 6. More...
#define	IRQ_MODE_CPU_7   (0x80UL << IRQ_MODE_CPU_Pos)
	CPU: interrupt targets CPU 7. More...
#define	IRQ_MODE_ERROR   (0x80000000UL)
	Bit indicating mode value error. More...

Description

The following codes are used as values for the parameter mode of the function IRQ_SetMode to configure interrupt line mode. They are also returned by the function IRQ_GetMode when retrieving interrupt line mode.

The values of IRQ_MODE_TRIG_x definitions specify The values of IRQ_MODE_TYPE_x definitions specify The values of IRQ_MODE_DOMAIN_x definitions specify The values of IRQ_MODE_CPU_x definitions specify

Interrupt mode bit-masks

Macro Definition Documentation

#define IRQ_MODE_CPU_0   (0x01UL << IRQ_MODE_CPU_Pos)

#define IRQ_MODE_CPU_1   (0x02UL << IRQ_MODE_CPU_Pos)

#define IRQ_MODE_CPU_2   (0x04UL << IRQ_MODE_CPU_Pos)

#define IRQ_MODE_CPU_3   (0x08UL << IRQ_MODE_CPU_Pos)

#define IRQ_MODE_CPU_4   (0x10UL << IRQ_MODE_CPU_Pos)

#define IRQ_MODE_CPU_5   (0x20UL << IRQ_MODE_CPU_Pos)

#define IRQ_MODE_CPU_6   (0x40UL << IRQ_MODE_CPU_Pos)

#define IRQ_MODE_CPU_7   (0x80UL << IRQ_MODE_CPU_Pos)

#define IRQ_MODE_CPU_ALL   (0x00UL << IRQ_MODE_CPU_Pos)

#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)

#define IRQ_MODE_DOMAIN_SECURE   (0x01UL << IRQ_MODE_DOMAIN_Pos)

#define IRQ_MODE_ERROR   (0x80000000UL)

#define IRQ_MODE_TRIG_EDGE   (0x04UL /*<< IRQ_MODE_TRIG_Pos*/)

#define IRQ_MODE_TRIG_EDGE_BOTH   (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)

#define IRQ_MODE_TRIG_EDGE_FALLING   (0x06UL /*<< IRQ_MODE_TRIG_Pos*/)

#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/)

#define IRQ_MODE_TRIG_LEVEL   (0x00UL /*<< IRQ_MODE_TRIG_Pos*/)

#define IRQ_MODE_TRIG_LEVEL_HIGH   (0x02UL /*<< IRQ_MODE_TRIG_Pos*/)

#define IRQ_MODE_TRIG_LEVEL_LOW   (0x01UL /*<< IRQ_MODE_TRIG_Pos*/)

#define IRQ_MODE_TYPE_FIQ   (0x01UL << IRQ_MODE_TYPE_Pos)

#define IRQ_MODE_TYPE_IRQ   (0x00UL << IRQ_MODE_TYPE_Pos)