CMSIS-Core (Cortex-A)
Version 1.1.4
CMSIS-Core support for Cortex-A processor-based devices
Main Page
Usage and Description
Reference
All
Data Structures
Files
Functions
Variables
Typedefs
Enumerations
Enumerator
Macros
Groups
Pages
Revision History of CMSIS-Core (Cortex-A)
Version
Description
V1.1.4
Fixed
__FPU_Enable()
.
V1.1.3
Fixed
__get_SP_usr()
/__set_SP_usr() for ArmClang.
Fixed zero argument handling in
__CLZ()
.
V1.1.2
Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.
Fixed co-processor register access macros for Arm Compiler 5.
V1.1.1
Refactored L1 cache maintenance to be compiler agnostic.
V1.1.0
Added compiler_iccarm.h for IAR compiler.
Added missing core access functions for Arm Compiler 5.
Aligned access function to coprocessor 15.
Additional generic Timer functions.
Bug fixes and minor enhancements.
V1.0.0
Initial Release for Cortex-A5/A7/A9 processors.
Generated on Fri Oct 25 2019 10:37:51 for CMSIS-Core (Cortex-A) Version 1.1.4 by Arm Ltd. All rights reserved.