Cadence Design Systems Inc. R8051XC (2 DPTR)

The Cadence Design Systems Inc. R8051XC (2 DPTR) is a flexible configurable, single-clock 8051 compatible IP core with 8 times more performance than the legacy 80C51 (with Dhrystone v1.1 Benchmark on identical clock speed). Features: 32 I/O lines, three 16-bit timer/counters, compare/capture unit (CCU), 18 interrupts/4 priority levels or 6 interrupts/2 priority levels, two serial interfaces (UARTs), serial peripheral interface (SPI), two I2C interfaces, 16-bit multiplication-division unit (MDU), multiple DPTR (1, 2 or 8) with auto-increment/auto-switch support, 15-bit programmable watchdog timer with configurable prescaler, power management unit (PMU), direct memory access (DMA) controller, real time clock (RTC), internally and externally generated wait states, software reset, program and data memory extension up to 8MB (banking). Optionally available: On-Chip Debug Support for Keil uVision Debugger or hooks for FS2 debug module. The R8051XC IP core can be implemented in FPGA and ASIC. *** This device is configured for 2 DPTR registers ***.

*** EOL Notice ***
This device is no longer in production.