Board Design Rules

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Consider the following guidelines when designing a board that supports ETM tracing:

1. Provide a 20-pin Cortex Debug+ETM connector for tracing, and place this connector as close as possible to the CPU.
2. Give serious considerations to high-speed signals coming from the ETM trace port, since they can have very fast rise and fall times even at low frequencies.
3. To minimize cross-talk, connect the TRACECLK and TRACEDATA[0..3] signals short and in parallel to each other.
4. Prevent pin-sharing conflicts on the ETM trace port pins. Often, TRACECLK and TRACEDATA[0..3] are shared with GPIOs, which means they cannot be used for tracing. Designers, anticipating the need for ETM tracing, should not use these pins for anything else.
5. Avoid tracks that tee off from the TRACECLK and TRACEDATA[0..3] signals, since they can cause impedance discontinuities affecting the signal quality.

The picture below is a sample board layout.

Note

• Good high-speed design practices should be followed. Books such as High-Speed Digital Design, by Dr. Howard W. Johnson and Dr. Martin Graham, cover these aspects.
• As an alternative to the 20-pin Cortex Debug+ETM connector, the 10-pin Cortex Debug connector can be used if ETM tracing is not required. The 20-pin Cortex Debug+ETM connector is a super-set of the 10-pin Cortex Debug. The first 10 pins are identical on both connectors.