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NAND Page Data LayoutNAND Page Data Layout describes the NAND driver structure, the data organization in a NAND Flash device page, and methods to change the data organization. The NAND driver configuration structure is defined in the file File_Config.h as follows: typedef struct { NAND_PG_LAY* PgLay; /* Page Layout Definitions */ U16 NumBlocks; /* Number of blocks per device */ U16 NumPages; /* Number of pages per block */ U16 PageSize; /* Page size */ U16 SectorsPerBlock; /* Number of sectors per block */ U8 SectorsPerPage; /* Number of sectors per page */ U8 AddrCycles; /* Device address cycles */ U8 SwEccEn; /* Software ECC enabled */ U8 DrvInst; /* Driver Instance definition */ } const NAND_DRV_CFG; The values set in the screen device configuration are propagated to this structure.
Page Layout StructureThe page layout structure is defined in the file File_Config.h as follows: typedef struct { U8 Pos_LSN; /* LSN position */ U8 Pos_COR; /* Data in page corrupted marker */ U8 Pos_BBM; /* Bad Block marker position */ U8 Pos_ECC; /* First byte of ECC */ U16 SectInc; /* Column increment till next sector */ U16 SpareOfs; /* Spare area offset from beginning */ /* of the page */ U16 SpareInc; /* Column increment till next spare */ } NAND_PG_LAY; This structure contains basic configuration info:
The default page data layout (defined by SectInc, SpareOfs and SpareInc values) contains a Spare area after each sector. Default 16-byte spare area data organization (defined by Pos_LSN, Pos_BBM and Pos_ECC values): Changing the default page data layoutThe NAND Flash device, or controller peripheral, can demand a different page data layout in order to calculate and store redundant error correction information. To alter the page data layout, overwrite the fields in the structure NAND_PG_LAY using the Init function. The spare area for OneNAND device is located after the last sector in a page: Page data layout example to support OneNAND devices: static U32 Init (NAND_DRV_CFG *cfg) { /* Setup OneNAND Page Layout */ cfg->PgLay->Pos_LSN = 2; cfg->PgLay->Pos_COR = 1; cfg->PgLay->Pos_BBM = 0; cfg->PgLay->Pos_ECC = 8; cfg->PgLay->SectInc = 512; cfg->PgLay->SpareOfs = 2048; cfg->PgLay->SpareInc = 16; /* Init NAND Driver Peripheral */ /* ... */ return RTV_NOERR; } | ||||||||||
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