Restrictions

When debugging on hardware, the number of items that can be defined in the Logic Analyzer is restricted by the microcontroller core (refer to Access Breakpoints in ULINK Debug Adapters). Many more different items can be defined in simulation mode.

The Logic Analyzer can record changes of:

• Global program variables, including struct members.
• VTREGs that represent I/O pins of the microcontroller.
• Peripheral registers that are triggered by external or internal events, but with the restrictions outlined below.

The Logic Analyzer cannot record changes of:

• Automatic variables defined inside a function
  Automatic variables are located on the stack or in overlayable memory regions. It is not possible to record changes of dynamic memory locations.
• CPU registers
  CPU registers cannot be triggered with read or write breakpoints. Therefore, such changes cannot be recorded.
• Peripheral registers that represent timer registers
  Increments of timers (or similar peripherals) are not simulated. Instead, the timing of events that are triggered by a timer, is calculated. Therefore, it is not possible to view timer increments.
• I/O pins of communication peripherals
  I/O pin toggling of UART, CAN, SPI, or I²C communication peripherals is not simulated. It is assumed that the timing of communication streams behaves according to the specifications. Instead, the I/O stream is represented by VTREGs.
• Memory BUS signals
  µVision simulates a CPU including memory areas, but it does not simulate the Memory BUS signals (data BUS, address BUS, and control lines like RD, WR, ALE). Therefore, it is not possible to view memory BUS signals with the Logic Analyzer.